#-- Synopsys, Inc.
#-- Version D-2009.12L Beta2
#-- Project file C:\paulshin\sw eval\ecp2m\good designs\ecp2m demo verilog core march 2010\run_options.txt
#-- Written on Fri Mar 05 09:26:43 2010


#project files
add_file -verilog "C:/ispTOOLS8_0sp1/ispcpld/../cae_library/synthesis/verilog/ecp2m.v"
add_file -verilog "./ECP2M_PRBS_SERDES_DEMO.h"
add_file -verilog "./dprom256x9.v"
add_file -verilog "./prbs7.v"
add_file -verilog "./pcs_10x.v"
add_file -verilog "./txrx_reset_sm.v"
add_file -verilog "./div2.v"
add_file -verilog "./top_demo.v"


#implementation: "ecp2m demo verilog core march 2010"
impl -add "ecp2m demo verilog core march 2010" -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0

#device options
set_option -technology LATTICE-ecp2m
set_option -part LFE2M50E
set_option -package F484C
set_option -speed_grade -5
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "top_demo"

# mapper_options
set_option -frequency 200
set_option -auto_constrain_io 1
set_option -write_verilog 1
set_option -write_vhdl 1

# Lattice XP
set_option -maxfan 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -forcegsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -update_models_cp 1

# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 1
set_option -resource_sharing 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./top_demo.edi"

#set log file 
set_option log_file "C:/paulshin/sw eval/ecp2m/good designs/ecp2m demo verilog core march 2010/top_demo.srf" 
impl -active "ecp2m demo verilog core march 2010"
